1) Field of the Invention
The present invention relates to technology for halting an information processing apparatus when a power source voltage supplied to the information processing apparatus which performs data write processing to a memory unit is lowered.
2) Description of the Related Art
Previously, an information processing apparatus which performs data writing to a memory forcibly resets a CPU (Central Processing Unit) or the like which performs data write processing when a power source voltage is lowered.
FIG. 5 shows a previous information processing apparatus 100. The information processing apparatus 100 has a voltage converting circuit 101, a memory 102, a battery 103, an arithmetic operation unit (for example, a CPU) 104, a memory controlling unit 105, and a voltage monitoring unit 106.
The voltage converting circuit 101 is a circuit which converts a power source voltage supplied from an external power source supplying unit 110 into a voltage used inside. Here, the voltage converting circuit 101 converts the power source voltage into an operable voltage for the memory 102, and supplies to the operable voltage to the memory 102.
Concretely, the voltage converting circuit 101 converts a power source voltage of 5.0 V, for example, from the external power source supplying unit 110 into 3.3 V, for example, and supplies the converted voltage to the memory 102. Further, the voltage converting circuit 101 converts a power source voltage of 5.0 V, for example, from the external power source supplying unit 110 into 3.3 V, for example, and supplies the converted voltage to the memory controlling unit 105.
The memory 102 is supplied with voltage from the voltage converting circuit 101 to hold data therein. The memory 102 holds data by using voltage of the battery 103, when power source supply from the external power source is lowered. The memory 102 is a memory unit which can perform battery backup.
In this instance, the memory 102 can perform write processing and read processing with a power source voltage of 3.0 V through 3.6 V. For example, the memory 102 can hold data with a power source voltage of 2.2 V through 3.6 V.
Further, the battery 103 is charged by receiving a power source voltage from the voltage converting circuit 101, while the information processing apparatus 100 is activated by the supply of power from the external power source supplying unit 110.
The arithmetic operation unit 104 issues a write request to perform data write processing to the memory 102, and operates with a power source voltage of 5.0 V supplied from an external power source supplying unit 110. In this instance, the arithmetic operation unit 104 is operable with a power source voltage of 4.5 V through 5.5 V.
The memory controlling unit 105 is supplied with voltage from the voltage converting circuit 101, and receives a data write request issued from the information processing apparatus 10, and controls (permits) data writing to the memory 102 based on the write request. In this instance, the memory controlling unit 105 is operable with a power source voltage of 3.0 V through 3.6 V, for example.
As shown in FIG. 5, the memory 102, the arithmetic operation unit 104 and the memory controlling unit 105 are connected via an address/data bus 107. For example, in the information processing apparatus 100, when the memory controlling unit 105 receives a write request (in the drawing, described as “write”), the memory controlling unit 105 sends a chip select signal and a write enable signal (in the drawing, described as “select/write enable signal”) to the memory 102. This makes it possible to write data to the memory 102. Data writing to the memory 102 is performed via the address/data bus 107.
The voltage monitoring circuit 106 is a circuit which monitors a power source voltage from the external power source supplying unit 110 (herein after, simply called a power source voltage). For example, a reference voltage (here, 4.2V) as a threshold value is input (not illustrated), and by comparing this reference voltage and the power source voltage, the voltage monitoring circuit 106 monitors lowering of the power source voltage. When the power source voltage becomes not higher than the reference voltage as shown in FIG. 6, for example, when a circuit breaker is off, and power failure occurs, the voltage monitoring circuit 106 resets the arithmetic operation unit 104 and the memory controlling unit 105.
Here, “reset” means deleting information which is being processed and held in the arithmetic operation unit 104 and the memory controlling unit 105, and halting the arithmetic operation unit 104 and the memory controlling unit 105.
In this instance, as technology equivalent to the previous art shown in FIG. 5, there is technology in which when the power voltage becomes lower than a predetermined voltage, a NMI (Non-Maskable Interrupt) signal to a CPU, and access to a RAM (Random Access memory) is prohibited to protect data held in the RAM (for example, see the following document 1). In addition, there is technology in which when an input voltage is lowered to a predetermined voltage, a reset signal is given to a micro processor to prohibit generating unjustifiable writing by the microprocessor and deleting to protect the memory (for example, see the following patent document 2).
Here, in the previous information processing apparatus 100 shown in FIG. 5 and the previous arts disclosed in following patent document 1 and 2, when a power source voltage becomes not higher than the reference voltage due to any cause such as power failure, regardless of processing state for the arithmetic operation unit 104 and the memory controlling unit 105, that is, even halfway through a bus cycle as write processing unit relating to a write request issued by the arithmetic operation unit 104, the voltage monitoring circuit 106 still resets the arithmetic operation unit 104 and the memory controlling unit 105, and thus, the arithmetic operation unit 104 and the memory controlling unit 105 is reset in asynchronous with the bus cycle.
That is, in the information processing apparatus 100 in which data is written to the memory 102 for each write request, the arithmetic operation unit 104 and the memory controlling unit 105 are reset halfway through writing of the write request from the arithmetic operation unit 104.
More specifically, as shown in FIG. 7(a), when it is detected that a power source voltage is lowered, and the voltage monitoring circuit 106 detects that the power source voltage becomes not higher than a reference voltage of 4.2 V (see range x indicated by the broken line in the drawing), as shown in FIG. 7(b), a reset signal is asserted (see timing t1; see range y indicated by the broken line in the drawing) to the arithmetic operation unit 104 and the memory controlling unit 105 asynchronously to a bus cycle relating to a write request from the arithmetic operation unit 104.
Here, in FIG. 7(b), “CPU-CLK” indicates a clock signal (for example, 25 MHz) input to the arithmetic operation unit 104; “CPU-ADD” indicates an address in the memory 102 to which data on an address bus is written; “-CPU-AS” indicates an address strove signal which indicates whether or not an address on the address bus is effective; “-BBRAM-CS” indicates a chip select signal output from the memory controlling unit 105 to the memory 102; “-BBRAM-WE” indicates a write enable signal output from the memory controlling unit 105 to the memory 102; “CPU-DATA” indicates data to be written to the memory 102 on the data bus. In this instance, as to the reset signal (“-RESET”) signal, the address strove signal (“-CPU-AS”), the chip select signal (“-BBRAM-CS”), and the write enable signal (“BBRAM-WE”), the lower side indicates ON (assert), and the upper side indicates OFF (negate).
Then, when the reset signal is asserted, the arithmetic operation unit 104 and memory controlling unit 105 are reset with that timing (see timing t1 in the drawing). Thus, halfway of a bus cycle (write processing unit for each write request), the address strove signal, the chip select signal, and the write enable signal change to negate, and the address bus and the data bus are also changed (see timing t1 in the drawing; see range z indicated by the broken line in the drawing).
On the other hand, at that time, since the memory 102 is in an operable state, depending on the chip select signal and the write enable signal as changed write controlling signals, and on address information on an address bus and a data state on data bus, unnecessary access to the memory 102 occurs, and thus, erroneous writing to the memory 102 can occur.
In particular, when the information processing apparatus 100 is such that referring to the memory 102 and is activated (boots up) based on the contents, if erroneous writing to the memory 102 occurs at the time of reset due to lowering of the power source voltage, it would happen that the next booting of the information processing apparatus 100 is impossible, and if the information processing apparatus 100 boots up, it can boot up in an erroneous state.
[Patent Document 1] Japanese Patent Application laid-open No. 2001-187252
[Patent Document 2] Japanese Patent Application laid-open No. SHO 59-206975